1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, in which base cells are arrayed in first and second directions perpendicular to each other, fabricated according to a master slice method or a standard cell method.
2. Description of the Related Art
FIG. 14(A) is a top view of a prior art base cell BCX in which gate lines are hatched (this applies to other figures).
The base cell BCX comprises an N-type well 10 indicated with a double dot and dash line, P-type diffused regions 11, 12 and 13 arrayed in a column direction and formed in the N-type well 10, and gate lines 14 and 15 formed above a channel between the P-type diffused regions 11 and 12 and above a channel between the P-type diffused regions 12 and 13, respectively, with a gate insulating film, for example a gate oxide film, interposed between each channel and gate line. Further, the base cell BCX comprises N+-type well contact regions 16 and 17 formed in the N-type well 10 in such a manner that they sandwich the P-type diffused regions 11 to 13 as a whole. Likewise, the base cell BCX comprises a P-type well 20 indicated with a double dot and dash line next to the N-type well 10, N type diffused regions 21, 22 and 23 arrayed in a column direction and formed in the P-type well 20, and gate lines 24 and 25 formed above a channel between the N-type diffused regions 21 and 22, and above a channel between the N-type diffused regions 22 and 23, respectively, with a gate insulating film interposed between each channel and gate line. P+-type well contact regions 26 and 27 are formed in the P-type well 20 in such a manner that they sandwich the N-type diffused regions 21 to 23 as a whole. At both ends of each of the gate lines 14, 15, 24 and 25, there are gate contact regions for connecting through interlayer contacts and conductive lines.
For example, one NAND gate with two-input is constituted of one base cell BCX with connecting conductive lines in the cell in a first wiring layer and power supply lines in a second wiring layer. The N+-type well contact regions 16 and 27 are connected to a power supply line VDD and a ground line VSS, respectively, in the second wiring layer above the first wiring layer. In FIG. 14(A), the VDD and VSS lines are represented by center lines thereof (a single dot and dash line) for simplicity.
Such base cells are arrayed in rows and columns on a semiconductor substrate to form, for example, a gate array according to a master slice method. In a row direction, base cells are arranged with no superimposition between adjacent cells. However, in a column direction, as shown in FIG. 14(B), base cells are arranged with superimposing well contact regions adjacent to each other in a design.
Cell pitches of the gate array in row and column directions are 10 G and 4 G, respectively, wherein G, for example, 0.8 mm denotes a pitch of a grid in design. Interconnections between cells are implemented in a third wiring layer above the second wiring layer. Automatic interconnection design using a computer is performed along grid lines.
Since the base cell BCX has the construction in which the N+-type well contact regions 16 and 17 are formed in the N-type well 10 in such a manner that they sandwich the P-type diffused regions 11 to 13, while the P+-type well contact regions 26 and 27 are formed in the P-type well 20 in such a manner that they sandwich the N-type diffused regions 21 to 23, a cell size is larger, thereby reducing a degree of integration.
Further, the well contact regions 17 and 26 are useless.
Connections between cells are mainly implemented by conductive lines in a column direction. However, connections in a column direction cannot be implemented in the second wiring layer since the power supply lines VDD and VSS are formed in a row direction in the second wiring layer.
FIG. 15(A) is a top view of another prior art base cell BCY.
In the base cell BCY, a gate line 34 serially passes above a channel between P-type diffused regions 11 and 12A and above a channel between N-type diffused regions 21 and 22A and similar to this, a gate line 35 serially passes above a channel between P-type diffused regions 12A and 13 and above a channel between N-type diffused regions 22A and 23. With these series of the gate lines, a cell pitch of a gate array in a row direction is (8G+G′) as shown in FIG. 15(B), and the cell pitch is shorter than that of 10G of FIG. 14(B) by (2G−G′). For example, when G=0.8 mm and G′=1.0 mm, 2G−G′=0.6 mm. The reason why the cell pitch of the gate array in the row direction is not 9G but (8G+G′) is that when cells are arrayed in the row direction, there arise a need to ensure a margin between adjacent gate contact regions, which is required from design rules.
Further, instead of the N+-type well contact regions 16 and 17 of FIG. 14(A), an N+-type well contact region 16A is formed in the N-type well 10 under a place between gate contact regions 341 and 351 formed at one ends of the gate lines 34 and 35, and similar to this, instead of the P+-type well contact regions 26 and 27 of FIG. 14(A), a P+-type well contact region 26A is formed in the P-type well 20 under a place between gate contact regions 342 and 352 formed at the other ends of the gate lines 34 and 35. Since there arise a need to ensure margins between the N+-type well contact region 16A and each of the gate contact regions 341 and 351, which is required from design rules, widths of the diffused regions 12A and 22A in a column direction are necessary to be wider than those of other diffused regions. Hence, a cell pitch of a gate array in a column direction is (2G+G′) as shown in FIG. 15(B). For this reason, a higher degree of integration was restricted.